1. Field of Invention
The present invention related to a method of fabricating capacitors which fabricates a plurality of capacitors of which capacitances are different one another on a semiconductor substrate.
2. Discussion of Related Art
In semiconductor devices, a memory device requires capacitors of which sizes are large for storing a lot of data. Thus, effective area for capacitance is increased by forming a three-dimensional structure such as the stacked, the trench-typed structure and the like to store large amount of data as well as the area occupied by an unit cell is reduced.
However, logic devices change impedance constantly according to frequencies of inputted signals which are operated by the signals which are constituted by digital and analog signals, thereby requiring no such capacitors as have large capacitance. Therefore, capacitors in logic devices are formed two-dimensionally on field oxide layers defining active areas of the devices. FIG. 1A to FIG. 1C show cross-sectional views of fabricating a capacitor according to a related art.
Referring to FIG. 1A, a field insulating layer 13 forming an active area of a device is formed in a field area on a semiconductor substrate 11. In this case, the field insulating layer 13 is formed by LOCOS(local oxidation of silicon) or STI(shallow trench isolation).
A first polysilicon layer 15 is formed on the semiconductor substrate 11 to cover the field insulating layer 13 by depositing polysilicon doped with impurities by CVD(hereinafter abbreviated CVD). And, a dielectric layer 17 having an ONO structure is formed by depositing silicon oxide, silicon nitride, and silicon oxide on the first polysilicon layer 15 successively by CVD. Referring to FIG. 1B, the dielectric layer 17 and first polysilicon layer 15 are patterned to expose the semiconductor substrate 11 and field insulating layer 13 by photolithography. In this case, the polysilicon layer 15 and the dielectric layer 17 which are not etched but remain become a lower electrode 16 of a capacitor and a dielectric, respectively.
A second polysilicon layer 18 is formed on the semiconductor substrate 11 by depositing polysilicon doped with impurities to cover the field insulating layer 13, lower electrode 16, and dielectric layer 17 by CVD.
Referring to FIG. 1C, an upper electrode 19 is formed by patterning the second polysilicon layer 18 only to remain on the dielectric layer 17 to expose the semiconductor substrate 11 and field insulating layer 13 by photolithography. Thus, the upper electrode 19 constitutes a capacitor with the lower electrode 16 and dielectric layer 17.
As mentioned in the above description, the related art fabricates a capacitor by forming a first polysilicon layer and a dielectric layer on a semiconductor substrate to cover a field insulating layer in order, by forming a lower electrode by means of patterning the layers by photolithography, by forming a second polysilicon layer on the semiconductor substrate to cover the lower electrode and dielectric layer, then by forming an upper electrode by means of patterning the second polysilicon layer to remain on the dielectric layer by photolithography.
Unfortunately, it is difficult to fabricate a plurality of capacitors of various capacitances on the same substrate in the related art because thickness of the dielectric layer is uniform.